In an inspection process of semiconductors, an electrical characteristics test is conducted by bringing probes having electrical conductivity into contact with the semiconductors in a state of a semiconductor wafer prior to dicing to detect a defective piece (a wafer-level testing). When the wafer-level testing is conducted, used for transmitting test signals to the semiconductor wafer is a probe card that houses a number of probes. The probe card includes a probe head that holds the probes, a space transformer that transforms minute wiring pitches between the probes in the probe head, and an interconnect substrate that connects the space transformer to an inspection device that outputs the test signals.
In the wafer-level testing, the probes are brought into contact with dies on the semiconductor wafer by the probe card scanning for each die individually. On the semiconductor wafer, however, a few hundreds to a few ten thousands of dies are formed. Thus, testing a single semiconductor wafer requires a considerable amount of time, thereby causing a rise in cost as the number of dies increases.
To resolve the above-described problems in the wafer-level testing, a method of collectively bringing a few hundreds to a few ten thousands of probes into contact with all of the dies on the semiconductor wafer or at least approximately a quarter to a half of the dies on the semiconductor wafer (a full wafer-level testing) has also been used recently (e.g., see Patent Literature 1). In this method, to bring the probes into contact with the electrodes on the semiconductor wafer correctly, known are technologies that maintain the accuracy of the positions of tips of the probes by accurately keeping the parallelism and flatness of the probe card with respect to the surface of the semiconductor wafer, and that align the semiconductor wafer with a high degree of accuracy (e.g., see Patent Literature 2 or Patent Literature 3).